The present invention relates to incorporating decoupling capacitance into a fin field effect transistor (FET) structure, and more specifically, to using a fin structure as a decoupling capacitor.
FinFET semiconductor technology provides improved transistor performance versus historic planar FET technologies. However, finFETs have much larger gate capacitances when compared to similar sized planar FETs. This increased gate capacitance can have negative effects on the power supplies used to provide the rail voltages to the finFETs which may cause the rail voltages to droop as the gates are switched. This droop can decrease the switching speed of the finFETs and negatively affect the overall timing of the semiconductor chip.